(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process sequence used top fabricate a FINFET device, a field effect transistor formed on an silicon on insulator (SOI) layer, with the mesa type device comprised with fin like features.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices comprised with sub-micron features, have allowed performance increases for devices comprised with the sub-micron features to be realized, while the manufacturing cost of a specific semiconductor chip formed with sub-micron features has been reduced. The decrease in performance degrading junction capacitance as a result of the use of sub-micron features, as well as the ability to obtain a greater number of semiconductor chips, still providing circuit densities comparable to counterpart semiconductor chips formed with larger features, have made the increased performance, and decreased fabrication cost objectives achievable. However as device features shrink specific parameters such as short channel effects, punch through, and leakage currents become more prevalent for devices formed with sub-micron features than for counterparts formed with larger features.
This invention will describe a process sequence in which device performance is further improved via additional decreases in junction capacitance via formation of the sub-micron type device on a silicon on insulator (SOI) layer of the device. A FINFET device defined in the SOI layer, with only the needed elements of the device now overlying the insulator layer of the SOI layer, results in a reduction in capacitance and thus increased performance when compared to counterpart FET devices fabricating within a semiconductor substrate and thus presenting higher parasitic junction capacitance. The ability to form the FINFET device on an SOI layer also reduces punch through leakage and short channel effects when compared to devices formed in a semiconductor substrate. However to maintain a narrow channel region for the mesa like FINFET device the portion of conductive material between the source and drain regions has to be minimized. This can result in unwanted channel resistance, adversely influencing device performance. Therefore a process and design for a FINFET device, reported in this present invention, will describe a necked channel region in which only a portion of conductive material located between the source and drain region will be necked or narrowed, while the other portions of the conductive region located between the source and drain regions will be wider thus minimizing the channel resistance of the FINFET device. In addition this invention will describe a procedure used to form a wrap up insulator spacer that will protect the exposed sides of the raised, FINFET device from a silicide procedure applied to source/drain regions. Prior art, such as Muller et al, in U.S. Pat. No. 6,252,284B1, Shirasaki, in U.S. Pat. No. 4,996,574, Yuzurihara et al, in U.S. Pat. No. 5,428,237, Burroughes et al, in U.S. Pat. No. 5,701,016, Kitajama, in U.S. Pat. No. 5,309,010, and Ohmi et al, in U.S. Pat. No. 6,242,783B1, describe methods of forming FINFET type devices, however none of these prior arts disclose the unique features of this invention, such as the necked channel region, and the wrap up insulator spacer.